Scientists have created the world’s tallest chip, composed of 41 layers. This “transistor skyscraper” overcomes the limitations of Moore’s Law, successfully boosting chip performance by six times.
The famous hypothesis that has long governed the rules of the semiconductor world and enabled rapid technological advancement states: chips become smaller, faster, and denser with each new generation. In 1965, when integrated circuits were still nascent, Gordon E. Moore predicted that the number of components on a single chip would approximately double every two years. Since then, much of our modern world—from computers and smartphones to cloud systems and massive data centers—has progressed following this logic of “scaling down to multiply.”
However, today, as transistors approach the atomic scale, this continuous shrinking game is hitting physical limits due to quantum effects. An international research team is now addressing this very threshold, suggesting that chips should be built upward, not horizontally.
A Design Different from Today’s Chips
This research introduces a new semiconductor chip design consisting of 41 layers, each containing 100 transistors. This density is about ten times greater than that previously reported in stacked hybrid chips, making it the tallest chip ever built. This revolutionary design increases circuit density by six-fold, enabling a performance boost without the need for further shrinking of the individual transistors.
Today, processors like AMD’s Ryzen 7 9800X3D can offer more cache by stacking chips on top of each other. Similarly, NAND memory used in SSDs is built with dozens of layers. However, these methods are fundamentally based on single-layer transistor arrays. The new method developed by KAUST is the first to overcome this limit by creating a multi-layer transistor structure within a single chip.
The team, led by KAUST researcher Xiaohang Li in Saudi Arabia, is providing a vertical solution to the physical limits approaching the semiconductor industry. According to the published study, the team produced a chip made of 41 semiconductor and insulator layers. In addition to being the tallest chip ever produced, this structure is poised to enable flexible, energy-efficient, and sustainable electronic systems.
Li states, “Vertically stacking six or more transistor layers allows us to increase circuit density without reducing the horizontal dimensions. With six layers, we can integrate 600% more logic functions into the same area compared to a single layer, thereby achieving higher performance and lower power consumption.”
Transistor Skyscrapers
The developed system is compared to a skyscraper. Just like these giant structures, each layer in the chips must be built with high precision. The research team developed new manufacturing strategies to resolve the issue of “interlayer roughness.” The researchers achieved a surface roughness of just 3.63 nanometers in layer alignment. This level of precision is critical to minimizing performance loss. The most crucial point was the low-temperature deposition of all layers at near room-temperature conditions.
This low-temperature manufacturing method is not just an engineering success; it also allows the use of flexible materials. Traditional semiconductor processes often exceed 400°C, which melts or degrades plastic or polymer-based materials. The new method eliminates this problem, allowing the safe use of plastic or polymer substrates, paving the way for flexible electronics.
450 Times Lower Energy Consumption!
To demonstrate the reliability of the design, the team produced 600 chips. All copies showed similar performance, while the power consumption was measured at only 0.47 microwatts. For comparison, the value in today’s advanced single-layer chips is around 210 microwatts. This means the new design can perform the same operations with approximately 450 times lower energy consumption.
Li notes that the technology will first be used in areas like wearable health sensors, smart tags, and flexible displays, where low energy consumption and mechanical flexibility are crucial. In the long term, researchers predict that it could enable new concepts such as large-area information processing systems or “electronic skins.” These systems could simultaneously perform data sensing, processing, and communication functions on the surface of objects or structures.
On the other hand, the new structure is not yet suitable for high-temperature processors, as the transistors can behave erratically above 50°C. This is why wearable technologies are the initial target.
Moore’s Law has long been cited as “approaching its end.” However, this approach by KAUST suggests that the law is not dead, but merely changing its “direction.”
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